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HD66130T
320-channel Low-voltage Segment Driver for Dot-Matrix STN Liquid Crystal Display
Description
The HD66130T is a 320-channel segment driver for driving a dot-matrix STN liquid-crystal panel at a low voltage. The driver can also correspond to 240-channel output by switching mode. It operates at a low voltage: a liquid-crystal drive voltage of 5 V and a logic drive voltage of 3 V, and is used together with common driver HD66131T or HD66135T. The package, which adopts a flexible TCP, can be applied to various liquid crystal panels.
Features
* * * * * * * * * * * * * Display duty: Up to 1/240 Liquid crystal drive voltage: 2.6 to 5.5 V Number of liquid crystal drive circuits: 320 circuits Operating voltage: 2.5 to 5.5 V Number of data bits: 4 or 8 bits Shift clock speed: 8 MHz max/5V 6.5 MHz max/3V Together with the common drivers HD66131T , HD66135T Low power consumption Switching output mode: 320 output mode 240 output mode Display-off function Flexible TCP Automatic generation of chip-enable signals Standby function
1
HD66130T
Pin Arrangement
316 Y316 317 Y317 318 Y318 319 Y319 Y320 320
V0L VML V1L
Y1 1
2 Y2 3 Y3 4 Y4 5 Y5
Top View
Note: TCP dimensions are not defined.
Internal Block Diagram
Y1-Y320
V0L VML V1L
VML V0L V1L VCC MODE BS GND2 SHL EIO1 DISP D0 D1 D2 D3 D4 D5 D6 D7 CL2 CL1 M EIO2 GND1 V1R V0R VMR
346 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 330 329 328 327 326 325 324 323 322 321
*
Liquid crystal drive circuit
Vcc GND2 GND1 CL1 M BS Data rearrangement circuit Timing generator circuit
Level shifter Level shifter Latch circuit 2
DISP
Latch circuit 1
Latch circuit 1
D0-D7 SHL MODE
CL2
Shift register
EIO1 EIO2 Note: Pins V0L, VML, and V1L are internally connected to pins V0R, VMR, and V1R, respectively.
2
HD66130T
1. Liquid crystal drive circuit Selects and outputs the liquid crystal drive level V0, VM, or V1 by DISP and a combination of data for latch circuit 2 and signal M. 2. Level shifter Converts logic signals to liquid crystal drive signals. 3. Latch circuit 2 320-bit latch circuit, which latches the data of latch circuits 1 at the fall of CL1 and outputs the data to the level shifter. 4. Latch circuit 1 4/8-bit parallel data latch circuit, which latches display data D0 to D7 according to signals transmitted from the shift register. 5. Shift register 80-bit shift register, which generates data-capture signals for latch circuits 1 at the fall of CL2. 6. Data rearrangement circuit Inverts the order of data output crosswise. 7. Timing generator circuit The timing generator circuit generates data latch pulses for latch circuit2 and changes pulse the LCD drive outputs to AC. HIFAS Family timing Comparision
HD66130/131/134/135 Input signal CL1 M Segment Common
HD66132/133
Output signal
3
HD66130T
Pin Functions
Class Power supply Pin Pin Symbol Number Name VCC GND1 GND2 343 324 340 VCC GND I/O -- Functions VCC-GND: Power supply for logic.
V0L, R 345, 322 V0L, R VML, R 346, 321 VML, R V1L, R 344, 323 V1L, R
Input Liquid crystal drive level power supply
V0 VM V1
Input Latch signal of display data: A liquid crystal drive signal corresponding to display data is output at the fall of CL1. Input Capture signal of display data: Display data is captured at the fall of CL2. Input A.C. signal of liquid crystal drive output
Display data Liquid crystal drive output Liquid crystal display 1 (Vcc level) Selected level ON OFF
Control signal
CL1 CL2 M
327 328 326
Clock 1 Clock 2 M
D0 to D7 336 to 329
DATA 0 Input to DATA 7
0 (GND level) Not-selected level
SHL EIO1
339 338
Shift Left Input Control signal for inverting the order of data output (see the following page) Enable IO1 I/O
SHL GND Vcc EI/O1 Enable input Enable output EI/O2 Enable output Enable input
EIO2
325
Enable IO2
I/O
Enable input: The enable input of the first IC is connected to the GND and another is connected to the enable output of the second IC. Enable output: Connected to the enable input of the second IC at cascade output.
DISP BS
337 341
Disp off Bus Select
Input Grounding DISP sets liquid crystal drive output Y1-Y320 to the VM level. Input Switches the number of input bits for the display data.
Vcc 8-bit input mode GND 4-bit input mode (Captures data from D0-D3. At this time, connect D4-D7 to the GND.)
MODE
342
MODE
Input Switches the number of input bits for the display data.
Vcc GND 320 output mode 240 output mode (Y41-Y280 are valid output. The other 80 pins output the not-selected-level signals synchronized every time; release these pins.)
4
HD66130T
Pin Functions (cont)
Class Pin Pin Symbol Number Name 1 to 320 Y1 to Y320 I/O Function
Liquid crystal Y1 to drive output Y320
Output Liquid crystal drive output: Selects and outputs level V0 or V1 according to the combination of the M signal and display data when DISP is connected to Vcc. M D Output level 1 V0 1 0 V1 1 V1 0 0 V0
5
HD66130T
Rearranging Output Data (SHL)
The order for the output of captured data is inverted crosswise according to the SHL signal. At this time, the input/output pin of the enable signal can be switched.
SHL = GND, BS = GND Y1 D3 Y2 D2 Y3 Y4 Y5 D3 Y6 Y7 Y8 D0 Y313 Y315 Y317 Y319 Y314 Y316 Y318 Y320 D3 D2 D1 D0 D3 D2 D1 D0
D1 D0
D2 D1
First data Enable input: EIO1 Enable output: EIO2
Last data
SHL = Vcc, BS = GND Y1 D0 Y2 D1 Y3 Y4 Y5 D0 Y6 Y7 Y8 D3 Y313 Y315 Y317 Y319 Y314 Y316 Y318 Y320 D0 D1 D2 D3 D0 D1 D2 D3
D2 D3
D1 D2
Last data Enable input: EIO2 Enable output: EIO1
First data
SHL = GND, BS = Vcc Y1 Y2 Y3 D5 Y4 Y5 Y6 D2 Y7 D1 Y8 D0 Y313 Y315 Y317 Y319 Y314 Y316 Y318 Y320 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6
D4 D3
First data Enable input: EIO1 Enable output: EIO2
Last data
SHL = Vcc, BS = Vcc Y1 Y2 Y3 D2 Y4 Y5 Y6 D5 Y7 D6 Y8 D7 Y313 Y315 Y317 Y319 Y314 Y316 Y318 Y320 D0 D1 D2 D3 D4 D5 D6 D7
D0 D1
D3 D4
Last data Enable input: EIO2 Enable output: EIO1
First data
6
HD66130T
Operation Timing
(1) 4-bit capture mode (1 line, 640 dots)
Line
CL2 1 D0 to D3 CL1 d1 d5
d313 d317
2 d8
79
80
81
82
159 160 161
d4
d316 d320
EIO2 (No. 1)
Data capture period for IC (No. 1)
EIO2 (No. 2)
Data capture period for IC (No. 2)
Y1-Y320
BS = GND (4-bit capture mode) During the data standby state when the data capture operation enable signal is low (SHL = GND: EIO1), the next data capture clock (CL2) cancels the standby state. The 4-bit data is captured at the fall of CL2. When 316 bits are captured, the enable signal becomes the GND level (SHL = GND: EIO2). When 320 bits are captured, the operation automatically stops (the standby state is entered). The second IC is then activated when pin EIO2 is connected to pin EIO1 of the second IC. Data output changes at the fall of CL1. During SHL = GND, captured data d1 and d320 are output to Y1 and Y320, respectively. During SHL = Vcc, data d1 and d320 are output to Y320 and Y1, respectively.
7
HD66130T
(2) 8-bit capture mode (1 line, 640 dots)
Line
CL2 1 D0 to D7 CL1
d1 d9
d305 d313
2
d16
39
40
41
42
79
80
d8
d312 d320
EIO2 (No. 1)
Data capture period for IC (No. 1)
EIO2 (No. 2)
Data capture period for IC (No. 2)
Y1-Y320
BS = Vcc (8-bit capture mode) The 8-bit display data is captured at the fall of CL2. Other basic operations are the same as those of the 4bit capture mode.
8
HD66130T
Application Example
The select COMMON driver
COMMON driver HD66131 (240OUT) HD66133 (120OUT) HD66135 (120OUT) select q x q
FLM CL1 M DISP D0-D7 CL2
Controller
Notes: 1. When designing the board, connect a capacitor near the IC to stabilize power supply. Use two capacitors of about 0.1 F for each IC (between Vcc and GND, V0 and GND, VLCD and GND, and VEE and GND). 2. In addition, for the power supply circuit, connect a capacitor of several F or several tens of F between the liquid crystal power supply and GND. For set evaluation, confirm that there is no inversion of liquid crystal drive power supply and level power supply in the period between when the liquid crystal drive power supply is turned on and when it is turned off. 3. Configuring the LCD panel using the HD66130 when using the select COMMON driver.
GND1,2 EIO2 M CL1 CL2 D0-D7 DISP EIO1 SHL BS MODE Vcc V1L, R V0L, R VML, R
GND1,2 EIO2 M CL1 CL2 D0-D7 DISP EIO1 SHL BS MODE Vcc V1L, R V0L, R VML, R
VLCD VH (COM) Vcc V0 (SEG) VM V1 (SEG) GND VL (COM) VEE
Power supply circuit
SEG1 SEG2 SEG3 SEG4 SEG5
Y320 to Y1 HD66130T
Y320 to Y1 HD66130T
SEG636 SEG637 SEG638 SEG639 SEG640
VLL, R VML, R VHL, R VLCDL, R VEEL, R DIO1 DISP SHL MWS4-0 M GND CL Vcc MODE
COM1 COM2 COM3 COM4 COM5
HD66131T
X240 to X1
LCD Panel 640 x 240 1/240 duty
COM236 COM237 COM238 COM239 COM240
9
HD66130T
Absolute Maximum Ratings
Item Power supply voltage for logic circuits Power supply voltage for LCD drive circuits Input voltage 1 Input voltage 2 Operating temperature Storage temperature Symbol VCC V0 VT1 VT2 Topr Tstg Rating -0.3 to + 7.0 -0.3 to + 7.0 -0.3 to VCC + 0.3 -0.3 to V0 + 0.3 -30 to +75 -55 to +110 Unit V V V V C C Notes 1, 4 1, 4 1, 2 1, 3, 4
Notes: 1. Potential from the GND 2. Applied to pins SHL, EIO1, EIO2, DISP, D0 to D7, CL1, CL2, M, BS, and MODE. 3. Applied to VML, VMR, V1L, and VMR. Operating the LSI in excess of the absolute maximum rating will result in permanent damage. Use the LSI observing electrical characteristic conditions in normal operation. Exceeding the conditions will cause malfunctions or will affect LSI reliability. 4. Conform to the following turn-on/off sequence of the power and signals. Otherwise, the LSI will malfunction or will be permanently damaged. In addition, LSI reliability will be affected.
Vcc
2.7 V
2.7 V
V0
0ms
0ms
VM VM V1
0ms
V1
0ms 0ms 0ms
DISP
Input-signal clock data Signal-undefined period Initialization period (at least one frame)
(0 ms: Minimum value)
10
HD66130T
4.1 Turning on the power 1) Turn on the power in the order of GND- VCC, GND-V0, and VM/V1. Then, ground the DISP pin. 2) The LCD forcibly outputs the VM level by the DISPOFF function. 3) Even if an input signal is disturbed immediately after VCC is applied, the DISPOFF function has priority. 4) Input the specific signal to initialize registers in the driver. The initialization period must be at least one frame. 5) The preparation of normal display is completed. Input the VCC level to the DISP pin to cancel the DISPOFF function. At this time, the level of pins V0, VM, and V1 must rise to the specific potential. 4.2 Turning off the power The procedure is basically the reverse for turning on the power. 1) Ground the DISP pin. 2) Turn off the liquid crystal power in the order of VM/V1 and GND-V0. 3) Ground VCC and an input signal. At this time, the level of pins V0, VM, and V1 must fall to 0 V. Since the DISPOFF function stops when VCC falls to 0 V, the LCD may output a level other than VM. Therefore, a display failure may occur when the power is turned off or on.
11
HD66130T
Electrical Characteristics
DC Characteristics 1 (VCC = 2.5 to 4.5V, V0-GND = 2.6 to 5.5V, Ta = -30 to +75C)
Item Input high voltage Symbol VIH Pins CL1, CL2, SHL, M, EIO1, EIO2, Min Typ Max VCC Unit Test Condition V Notes
0.8 x V CC --
Input low voltage
VIL
MODE, 0 DISP, D0 to D7, BS EIO1, EIO2 EIO1, EIO2 VCC -0.4 --
--
0.2 x V CC
V
Output high voltage Output low voltage Vi-Yj on resistance
VOH VOL RON
-- -- 0.7
-- 0.4 2.0
V V k
I OH = -0.4 mA I OL = 0.4 mA I ON = 150 A 1
Y1 to -- Y320, V0L, R Y1 to -- Y320, VML, R Y1 to -- Y320, V1L, R
2.0
3.0
k
0.7
2.0
k
Input leakage current 1
I IL1
-5.0 CL1, CL2, SHL, M, EIO1, EIO2, MODE, DISP, D0 to D7, BS VML, -25 R, V1L, R VCC --
5.0
A
VIN = VCC to GND
Input leakage current 2
I IL2
25
A
VIN = V0 to GND
Current consumption 1 Current consumption 2 Current consumption 3
I CC IV0 I ST
150 300 60 50 200 100
A A A
VCC = 3.3 V V0 = 2.7 V f CL2 = 3.5 MHz f CL1= 19.2 kHz fM = 1.5 kHz
2
V0L, R -- VCC --
2, 3
12
HD66130T
DC Characteristics 2 (VCC = 4.5 to 5.5V, V0-GND = 2.6 to 5.5V, Ta = -30 to +75C)
Item Input high voltage Symbol VIH Pins CL1, CL2, SHL, M, EIO1, EIO2, Min Typ Max VCC Unit Test Condition V Notes
0.8 x V CC --
Input low voltage
VIL
MODE, 0 DISP, D0 to D7, BS EIO1, EIO2 EIO1, EIO2 VCC -0.4 --
--
0.2 x V CC
V
Output high voltage Output low voltage Vi-Yj on resistance
VOH VOL RON
-- -- 0.7
-- 0.4 2.0
V V k
I OH = -0.4 mA I OL = 0.4 mA I ON = 150 A 1
Y1 to -- Y320, V0L, R Y1 to -- Y320, VML, R Y1 to -- Y320, V1L, R
2.0
3.0
k
0.7
2.0
k
Input leakage current 1
I IL1
-5.0 CL1, CL2, SHL, M, EIO1, EIO2, MODE, DISP, D0 to D7, BS VML, -25 R, V1L, R VCC --
5.0
A
VIN = VCC to GND
Input leakage current 2
I IL2
25
A
VIN = V0 to GND
Current consumption 1 Current consumption 2 Current consumption 3
I CC IV0 I ST
230 450 60 80 200 150
A A A
VCC = 5.0 V V0 = 2.7 V f CL2 = 3.5 MHz f CL1= 19.2 kHz fM = 1.5 kHz
2
V0L, R -- VCC --
2, 3
Notes: 1. Resistance between pins Y and V when a load current flows to one of the pins from Y1 to Y320. The following conditions are defined: V0-GND = 5.5 V VM = (V0 + V1)/2
13
HD66130T
V1 = GND + 1.0 The voltage range of the liquid crystal drive level power supply is described. A voltage around the GND is applied to pin V1, and an intermediate voltage of about V0 and V1 is applied to pin VM. Use the V1 in the range of V = 0.25 x V0, in which the impedance Ron of driver output is stable.
V0
VM V = 0.25 x V0
V1 GND
Relationship between the driver output waveform and each level voltage 2. A current flowing in the input or output section is excluded. If an input signal is at an intermediate level for the CMOS, a through-current flows in the input circuit and power supply current increases. Therefore, VIH must be at the Vcc level and VIL must be at the GND level. 3. Current at standby 4. The voltage of each signal is shown below.
Segment voltage Segment waveform Common waveform Common voltage VH (23.0 V)
V0 (5.0 V) Vcc (3.3 V) VM (3.0 V) V1 (1.0 V) GND (0.0 V) Vcc (3.3 V) VM (3.0 V)
GND (0.0 V)
VL (-17.0 V) Normal display period Display-off period Normal display period Display-off period
14
HD66130T
AC Characteristics 1 (VCC = 2.5 to 4.5V, V0-GND = 2.6 to 5.5V, Ta = -30 to +75C)
Item Clock cycle time Clock high pulse width 1 Clock low pulse width 1 Clock high pulse width 2 Clock setup time Clock hold time Clock rise time Clock fall time Data setup time Data hold time M setup time M hold time Output delay time 1 Symbol t CYC t CWH2 t CWL2 t CWH1 t SCL t HCL tr tf t DS t DH t MS t MH t pd1 Pins CL2 CL2 CL2 CL1 CL1, CL2 CL1, CL2 CL1, CL2 CL1, CL2 D0 to D7, CL2 D0 to D7, CL2 M, CL1 M, CL1 CL1, Y1 to Y320 Min 152 65 65 65 80 80 -- -- 50 50 20 20 -- Max -- -- -- -- -- -- 30 30 -- -- -- -- 1000 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
AC Characteristics 2 (VCC = 4.5V to 5.5V, V0-GND = 2.6 to 5.5V, Ta = -30 to +75C)
Item Clock cycle time Clock high pulse width 1 Clock low pulse width 1 Clock high pulse width 2 Clock setup time Clock hold time Clock rise time Clock fall time Data setup time Data hold time M setup time M hold time Symbol t CYC t CWH2 t CWL2 t CWH1 t SCL t HCL tr tf t DS t DH t MS t MH Pins CL2 CL2 CL2 CL1 CL1, CL2 CL1, CL2 CL1, CL2 CL1, CL2 D0 to D7, CL2 D0 to D7, CL2 M, CL1 M, CL1 Min 125 45 45 45 80 80 -- -- 20 20 20 20 Max -- -- -- -- -- -- 20 20 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Output delay time 1 t pd1 CL1, Y1 to Y320 -- 1000 Notes: 1. A load must be 10 pF or less for EI/O connection between drivers. 2. For output delay time 1 and 2, connect the load circuit shown below.
Test point 100 pF
15
HD66130T
tr tCWH2 tf tCWL2 tCYC
0.8 Vcc
CL2
0.2 Vcc tDS 0.8 Vcc 0.2 Vcc tDH
D0-7
tCWH1 0.8 Vcc
CL1
tSCL
0.2 Vcc tHCL
CL2
0.2 Vcc tMS tMH 0.8 Vcc
M
0.2 Vcc
CL1
0.2 Vcc tpd1
Y (n)
0.8 V0 0.2 V1
16

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